IRQ
The IRQ status bits are as follows:
| Bit | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
|---|---|---|---|---|---|---|---|---|
| Description | Unused | SPI | SDRAM | Switch | Rotary | VSYNC | HSYNC | Reset |
The IRQ mask is logically ANDed with the IRQ status, and the IRQ signal is the logical OR of each of the resultant value.
HSYNC/VSYNC
These are set to 1 when an HSYNC or a VSYNC have occurred.
Rotary/Switch
The rotary IRQ is generated when the rotary encoder is turned. The switch IRQ is generated when one of the switches is pressed.
SDRAM
This is set when the SDRAM is ready (about 200µs after initialisation).
SPI
This is set when the SPI transfer has completed.