State machines

Here are the state machine diagrams for the elements that have state machines.

Interconnect (and CPU interface)

Interconnect state machine

This is the most complex state machine, with 13 different states (excluding the reset state). It performs the routing of data between the modules and the CPU, but does not perform any arbitration.

The priority for leaving the idle state is:

  1. (is_write = 1)
    1. (addr[3] == 1'b0) SetInternal
    2. (addr[3:0] == 4'b1000) SRAccess
    3. (addr[3:0] == 4'b1111) CLUTAccess
    4. (addr[3:0] == 4'b1110) AddAddr
    5. (addr[3:0] == 4'b1001) SDAccess
    6. (addr[3:0] == 4'b1011) VGenAccess
    7. (addr[3:1] == 3'b110) MMUAccess
    8. (addr[3:0] == 3'b1010) SPIAccess
    9. Otherwise WriteEnd
  2. (is_read = 1)
    1. (addr[3] == 1'b0) GetInternal
    2. (addr[3:0] == 4'b1000) SRAccess
    3. (addr[3:1] == 3'b110) MMUaccess
    4. (addr[3:0] == 4'b1110) RotClear
    5. (addr[3:0] == 4'b1001) SDAccess
    6. (addr[3:0] == 4'b1010) SPIAccess
    7. Otherwise ReadEnd

These states are actually mutually exclusive, so the ordering has no bearing (except the otherwise ones - although the is_write otherwise will never be reached, since all write states are accounted for).

SRAM and LCD

SRAM and LCD state machine

Since the LCD interface uses the SRAM, access from the CPU and the LCD need to be arbitrated - and this is done here. LCD data has the highest priority.

SDRAM initialisation

SDRAM initialisation state machine

This is the initialisation state machine - the SDRAM cannot be used until this has been completed.

The Wait200 state waits for 200us, and then a precharge-all command is issued, followed by two auto-refreshes and finally the set mode register command. All the commands have a number of wait states between them.

SDRAM data access

SDRAM data access state machine

This performs arbitration between effectively three sources - two CPU interfaces (one of which is the voice generator, and the other is the main CPU), and the internal refresh. The refresh has the highest priority, as it must be done as often as necessary. The voice generator has the next priority, and finally the CPU has the lowest priority (an additional state is used to switch the address, data and write lines over to the CPU - by default, the voice generator is selected).

Updated: 2011-06-08 20:39:29 | Comments: 0 | Show comments | Add comment
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