The IRQ status bits are as follows:

Bit 0706050403020100
Description Unused SPI SDRAM Switch Rotary VSYNC HSYNC Reset

The IRQ mask is logically ANDed with the IRQ status, and the IRQ signal is the logical OR of each of the resultant value.


These are set to 1 when an HSYNC or a VSYNC have occurred.


The rotary IRQ is generated when the rotary encoder is turned. The switch IRQ is generated when one of the switches is pressed.


This is set when the SDRAM is ready (about 200µs after initialisation).


This is set when the SPI transfer has completed.

Updated: 2011-06-08 20:39:29 | Comments: 0 | Show comments | Add comment
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